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ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 2 months ago
A Scalable Instruction Queue Design Using Dependence Chains
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
Steven E. Raasch, Nathan L. Binkert, Steven K. Rei...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 2 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
AINA
2010
IEEE
15 years 2 months ago
The Cost Effective Pre-processing Based NFA Pattern Matching Architecture for NIDS
—Network Intrusion Detection System (NIDS) is a system which can detect network attacks resulted from worms and viruses on the Internet. An efficient pattern matching algorithm p...
Yeim-Kuan Chang, Chen-Rong Chang, Cheng-Chien Su
FPL
2001
Springer
96views Hardware» more  FPL 2001»
15 years 2 months ago
System Level Tools for DSP in FPGAs
Abstract. Visual data ow environments are ideally suited for modeling digital signal processing (DSP) systems, as many DSP algorithms are most naturally speci ed by signal ow gra...
James Hwang, Brent Milne, Nabeel Shirazi, Jeffrey ...
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
15 years 2 months ago
Cycle-accurate macro-models for RT-level power analysis
 In this paper we present a methodology and techniques for generating cycle-accurate macro-models for RTlevel power analysis. The proposed macro-model predicts not only...
Qinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding