376 search results - page 6 / 76 » Improved Simulation of Stabilizer Circuits |
TCAD
1998
14 years 9 months ago
1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a cmos circuit under a general delay model. This technique is based on the noti...
CCE
2005
14 years 9 months ago
2005
Armed with increasingly fast supercomputers and greater knowledge of the molecular mechanisms of gene expression, it is now practical to numerically simulate complex networks of r...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
DSD
2010
IEEE
14 years 8 months ago
2010
IEEE
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...
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ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
— Negative Bias Temperature Instability (NBTI) has the potential to become one of the main show-stoppers of circuit reliability in nanometer scale devices due to its deleterious ...