376 search results - page 74 / 76 » Improved Simulation of Stabilizer Circuits |
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip...
104
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TCAD
2011
14 years 4 months ago
2011
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
ISCA
2007
IEEE
15 years 4 months ago
2007
IEEE
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
Statistical static timing analysis (SSTA) is emerging as a solution for predicting the timing characteristics of digital circuits under process variability. For computing the stat...
111
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GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...