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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
15 years 3 months ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
ICN
2007
Springer
15 years 4 months ago
Heuristic Approach of Optimal Code Allocation in High Speed Downlink Packet Access Networks
— In this paper, we use the Markov Decision Process (MDP) technique to find the optimal code allocation policy in High-Speed Downlink Packet Access (HSDPA) networks. A discrete ...
Hussein Al-Zubaidy, Jerome Talim, Ioannis Lambadar...
84
Voted
ANCS
2005
ACM
15 years 3 months ago
Group round robin: improving the fairness and complexity of packet scheduling
We present Group Round-Robin (GRR) scheduling, a hybrid fair packet scheduling framework based on a grouping strategy that narrows down the traditional trade-off between fairness ...
Bogdan Caprita, Jason Nieh, Wong Chun Chan
85
Voted
COMCOM
2004
110views more  COMCOM 2004»
14 years 10 months ago
On the latency and fairness characteristics of pre-order deficit round Robin
In the emerging high-speed packet-switched networks, fair packet scheduling algorithms in switches and routers will form an important component of the mechanisms that seek to sati...
Salil S. Kanhere, Harish Sethu