59 search results - page 4 / 12 » Improved indexing for cache miss reduction in embedded syste... |
CASES
2008
ACM
13 years 8 months ago
2008
ACM
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
CODES
2001
IEEE
13 years 10 months ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
In embedded system-on-a-chip (SoC) applications, the need for integrating heterogeneous processors in a single chip is increasing. An important issue in integrating heterogeneous ...
ECRTS
2009
IEEE
13 years 4 months ago
2009
IEEE
While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access p...
ISCA
1993
IEEE
13 years 10 months ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...