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» Improved procedure placement for set associative caches
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DATE
2010
IEEE
153views Hardware» more  DATE 2010»
15 years 2 months ago
HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling
— This paper describes a Model Order Reduction algorithm for multi-dimensional parameterized systems, based on a sampling procedure which incorporates a low order moment matching...
Jorge Fernandez Villena, Luis Miguel Silveira
ICASSP
2010
IEEE
14 years 10 months ago
Multipass strategies for improving accuracy in a voice search application
This paper describes a set of techniques for improving the performance of automated voice search services intended for mobile users accessing these services over a range of portab...
Tianhe Zhang, Richard Rose, Jean Dahan
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
15 years 6 months ago
Counter-Based Cache Replacement Algorithms
Recent studies have shown that in highly associative caches, the performance gap between the Least Recently Used (LRU) and the theoretical optimal replacement algorithms is large,...
Mazen Kharbutli, Yan Solihin
ICS
2003
Tsinghua U.
15 years 3 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
LCTRTS
2007
Springer
15 years 3 months ago
Integrated CPU and l2 cache voltage scaling using machine learning
Embedded systems serve an emerging and diverse set of applications. As a result, more computational and storage capabilities are added to accommodate ever more demanding applicati...
Nevine AbouGhazaleh, Alexandre Ferreira, Cosmin Ru...