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» Improved procedure placement for set associative caches
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PCI
2005
Springer
15 years 3 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
MONET
2008
77views more  MONET 2008»
14 years 9 months ago
On Relay Node Placement and Assignment for Two-tiered Wireless Networks
Wireless networks that operate on batteries are imposed with energy constraints and long distance communications between nodes are not desirable. Implementing Relay Nodes (RNs) can...
Wenxuan Guo, Xin-Ming Huang, Wenjing Lou, Cao Lian...
MTA
2006
115views more  MTA 2006»
14 years 9 months ago
Cache modeling and optimization for portable devices running MPEG-4 video decoder
Abstract There are increasing demands on portable communication devices to run multimedia applications. ISO (an International Organization for Standardization) standard MPEG-4 is a...
Abu Asaduzzaman, Imad Mahgoub
JMLR
2008
159views more  JMLR 2008»
14 years 9 months ago
Near-Optimal Sensor Placements in Gaussian Processes: Theory, Efficient Algorithms and Empirical Studies
When monitoring spatial phenomena, which can often be modeled as Gaussian processes (GPs), choosing sensor locations is a fundamental task. There are several common strategies to ...
Andreas Krause, Ajit Paul Singh, Carlos Guestrin
FPL
1997
Springer
125views Hardware» more  FPL 1997»
15 years 1 months ago
VPR: A new packing, placement and routing tool for FPGA research
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
Vaughn Betz, Jonathan Rose