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IWMM
2009
Springer
130views Hardware» more  IWMM 2009»
15 years 4 months ago
A component model of spatial locality
Good spatial locality alleviates both the latency and bandwidth problem of memory by boosting the effect of prefetching and improving the utilization of cache. However, convention...
Xiaoming Gu, Ian Christopher, Tongxin Bai, Chengli...
ISQED
2000
IEEE
91views Hardware» more  ISQED 2000»
15 years 2 months ago
Probabilistic Bottom-Up RTL Power Estimation
We address the problem of power estimation at the register-transfer level (RTL). At this level, the circuit is described in terms of a set of interconnected memory elements and co...
Ricardo Ferreira, A.-M. Trullemans, José C....
JUCS
2000
120views more  JUCS 2000»
14 years 9 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
JSAC
2007
105views more  JSAC 2007»
14 years 9 months ago
What and how much to gain by spectrum agility?
— Static spectrum allocation prohibits radio devices from using spectral bands designated for others. As a result, some bands are under-utilized while other bands are over-popula...
Chun-Ting Chou, Sai Shankar N., Hyoil Kim, Kang G....
LCTRTS
2007
Springer
15 years 4 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier