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EUROPAR
2010
Springer
15 years 6 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
16 years 19 days ago
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
LCN
2005
IEEE
15 years 11 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
PADS
2003
ACM
15 years 11 months ago
HLA-based Adaptive Distributed Simulation of Wireless Mobile Systems
Wireless networks’ models differ from wired ones at least in the innovative dynamic effects of host-mobility and open-broadcast nature of the wireless medium. Topology changes d...
Luciano Bononi, Gabriele D'Angelo, Lorenzo Donatie...
ASPLOS
2004
ACM
15 years 11 months ago
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign
Tracing garbage collectors traverse references from live program variables, transitively tracing out the closure of live objects. Memory accesses incurred during tracing are essen...
Chen-Yong Cher, Antony L. Hosking, T. N. Vijaykuma...