Sciweavers

555 search results - page 90 / 111
» Improved results for a memory allocation problem
Sort
View
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
15 years 3 months ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
SBACPAD
2003
IEEE
135views Hardware» more  SBACPAD 2003»
15 years 3 months ago
Adaptive Compressed Caching: Design and Implementation
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
Rodrigo S. de Castro, Alair Pereira do Lago, Dilma...
ICPP
1999
IEEE
15 years 2 months ago
A Framework for Interprocedural Locality Optimization Using Both Loop and Data Layout Transformations
There has been much work recently on improving the locality performance of loop nests in scientific programs through the use of loop as well as data layout optimizations. However,...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...
ASPLOS
1998
ACM
15 years 2 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...
AI
2000
Springer
14 years 9 months ago
Proving theorems by reuse
We investigate the improvement of theorem proving by reusing previously computed proofs. We have developed and implemented the PLAGIATOR system which proves theorems by mathematic...
Christoph Walther, Thomas Kolbe