1792 search results - page 332 / 359 » Improved scheduling in rings |
ISCA
2010
IEEE
15 years 4 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
HPCA
2000
IEEE
15 years 3 months ago
2000
IEEE
This paper presents flit-reservation flow control, in which control flits traverse the network in advance of data flits, reserving buffers and channel bandwidth. Flit-reservation ...
116
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DAC
1998
ACM
15 years 3 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
SPAA
1997
ACM
15 years 3 months ago
1997
ACM
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...
105
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DATE
2004
IEEE
15 years 2 months ago
2004
IEEE
Code optimization and high level synthesis can be posed as constraint satisfaction and optimization problems, such as graph coloring used in register allocation. Graph coloring is...