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» Improvement of ASIC Design Processes
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CANPC
1999
Springer
15 years 10 months ago
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
David Brooks, Margaret Martonosi
215
Voted
POPL
1989
ACM
15 years 10 months ago
How to Make ad-hoc Polymorphism Less ad-hoc
raction that a programming language provides influences the structure and algorithmic complexity of the resulting programs: just imagine creating an artificial intelligence engine ...
Philip Wadler, Stephen Blott
156
Voted
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 10 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...
DATE
2004
IEEE
144views Hardware» more  DATE 2004»
15 years 9 months ago
A Framework for Battery-Aware Sensor Management
A distributed sensor network (DSN) designed to cover a given region R, is said to be alive if there is at least one subset of sensors that can collectively cover (sense) the regio...
Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chop...
ESCIENCE
2006
IEEE
15 years 9 months ago
Scientific Workflows: More e-Science Mileage from Cyberinfrastructure
We view scientific workflows as the domain scientist's way to harness cyberinfrastructure for e-Science. Domain scientists are often interested in "end-to-end" fram...
Bertram Ludäscher, Shawn Bowers, Timothy M. M...