2669 search results - page 339 / 534 » Improvement of a configuration management system |
117
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TC
2008
15 years 1 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
118
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ACMSE
2009
ACM
15 years 8 months ago
2009
ACM
Most modern microprocessor-based systems provide support for superpages both at the hardware and software level. Judicious use of superpages can significantly cut down the number...
101
Voted
SIGMETRICS
2010
ACM
15 years 6 months ago
2010
ACM
We present RSIO, a processor scheduling framework for improving the response time of latency-sensitive applications by monitoring accesses to I/O channels and inferring when user ...
142
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LCTRTS
2010
Springer
14 years 11 months ago
2010
Springer
In this paper, we propose a hybrid-level flash translation layer (FTL) called RNFTL (Reuse-Aware NFTL) to improve the endurance and space utilization of NAND flash memory. Our bas...
206
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FPGA
2011
ACM
14 years 5 months ago
2011
ACM
FPGAs have been used in many applications to achieve orders-of-magnitude improvement in absolute performance and energy efficiency relative to conventional microprocessors. Despit...