24 search results - page 3 / 5 » Improvements for the Symbolic Verification of Timed Automata |
CHARME
2003
Springer
15 years 1 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
102
Voted
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
Abstract-- Image computation is the core operation for optimization and formal verification of sequential systems like controllers or protocols. State exploration techniques based ...
ACSD
2007
IEEE
14 years 11 months ago
2007
IEEE
We present an improvement of the SAT-based Unbounded Model Checking (UMC) algorithm. UMC, a symbolic approach introduced in [7], uses propositional formulas in conjunctive normal ...
ISSRE
2010
IEEE
14 years 8 months ago
2010
IEEE
— With the increasing reliance of complex real-world applications on composite web services assembled from independently developed component services, there is a growing need for...