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» Improving Exploration in UCT Using Local Manifolds
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ASPLOS
2006
ACM
15 years 5 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
CODES
2005
IEEE
15 years 4 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
INFOCOM
2010
IEEE
14 years 9 months ago
Joint Energy Management and Resource Allocation in Rechargeable Sensor Networks
—Energy harvesting sensor platforms have opened up a new dimension to the design of network protocols. In order to sustain the network operation, the energy consumption rate cann...
Ren-Shiou Liu, Prasun Sinha, Can Emre Koksal
WWW
2008
ACM
15 years 11 months ago
Geographic web usage estimation by monitoring DNS caches
DNS is one of the most actively used distributed databases on earth, accessed by millions of people every day to transparently convert host names into IP addresses and vice versa....
Hüseyin Akcan, Torsten Suel, Hervé Br&...
ICS
1999
Tsinghua U.
15 years 3 months ago
Software trace cache
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...