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» Improving FPGA Performance for Carry-Save Arithmetic
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ACIVS
2006
Springer
14 years 11 days ago
Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images
We present a novel dedicated hardware system for the extraction of second-order statistical features from high-resolution images. The selected features are based on gray level co-o...
Dimitris G. Bariamis, Dimitrios K. Iakovidis, Dimi...
IJNSEC
2010
247views more  IJNSEC 2010»
13 years 1 months ago
Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and imp...
Sameh M. Shohdy, Ashraf El-Sisi, Nabil A. Ismail
CODES
2005
IEEE
14 years 19 hour ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...