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HPCA
2011
IEEE
14 years 5 months ago
ACCESS: Smart scheduling for asymmetric cache CMPs
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...
Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishanka...
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HPCA
2011
IEEE
14 years 5 months ago
Beyond block I/O: Rethinking traditional storage primitives
Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have de...
Xiangyong Ouyang, David W. Nellans, Robert Wipfel,...
ICASSP
2011
IEEE
14 years 5 months ago
Exemplar-based Sparse Representation phone identification features
Exemplar-based techniques, such as k-nearest neighbors (kNNs) and Sparse Representations (SRs), can be used to model a test sample from a few training points in a dictionary set. ...
Tara N. Sainath, David Nahamoo, Bhuvana Ramabhadra...
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
14 years 4 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
BMCBI
2011
14 years 4 months ago
To aggregate or not to aggregate high-dimensional classifiers
Background: High-throughput functional genomics technologies generate large amount of data with hundreds or thousands of measurements per sample. The number of sample is usually m...
Cheng-Jian Xu, Huub C. J. Hoefsloot, Age K. Smilde