2194 search results - page 325 / 439 » Improving HLRTA*( k ) |
113
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IPPS
2000
IEEE
15 years 5 months ago
2000
IEEE
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
177
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SC
2000
ACM
15 years 5 months ago
2000
ACM
We aimed to study the performance of a parallel implementation of an intraoperative nonrigid registration algorithm that accurately simulates the biomechanical properties of the b...
123
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ICCAD
1999
IEEE
15 years 5 months ago
1999
IEEE
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
ISPASS
2007
IEEE
15 years 7 months ago
2007
IEEE
We have studied DRAM-level prefetching for the fully buffered DIMM (FB-DIMM) designed for multi-core processors. FB-DIMM has a unique two-level interconnect structure, with FB-DIM...
101
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COCO
2007
Springer
15 years 7 months ago
2007
Springer
We consider the k-layer pointer jumping problem in the one-way multi-party number-on-the-forehead communication model. Sufficiently strong lower bounds for the problem would have...