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» Improving Java performance using hardware translation
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DATE
2009
IEEE
132views Hardware» more  DATE 2009»
15 years 11 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...
ISCA
2010
IEEE
247views Hardware» more  ISCA 2010»
15 years 8 months ago
An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Sunpyo Hong, Hyesoon Kim
166
Voted
ISCA
2003
IEEE
93views Hardware» more  ISCA 2003»
15 years 10 months ago
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors
This work examines dynamic cluster assignment for a clustered trace cache processor (CTCP). Previously proposed cluster assignment techniques run into unique problems as issue wid...
Ravi Bhargava, Lizy Kurian John
CAL
2010
15 years 2 months ago
A Case for Alternative Nested Paging Models for Virtualized Systems
Address translation often emerges as a critical performance bottleneck for virtualized systems and has recently been the impetus for hardware paging mechanisms. These mechanisms ap...
Giang Hoang, Chang Bae, Jack Lange, Lide Zhang, Pe...
ISQED
2005
IEEE
140views Hardware» more  ISQED 2005»
15 years 10 months ago
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New...
Aaron N. Ng, Igor L. Markov