To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
—This paper evaluates techniques for improving operating system and network protocol software support for high-performance World Wide Web servers. We study approaches in three ca...
Erich M. Nahum, Tsipora P. Barzilai, Dilip D. Kand...
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
Sawal Ali, Reuben Wilcock, Peter R. Wilson, Andrew...
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes br...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...