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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 10 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
PACS
2000
Springer
132views Hardware» more  PACS 2000»
15 years 8 months ago
An Adaptive Issue Queue for Reduced Power at High Performance
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
Alper Buyuktosunoglu, Stanley Schuster, David Broo...
137
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CIDR
2007
116views Algorithms» more  CIDR 2007»
15 years 6 months ago
Managing Query Compilation Memory Consumption to Improve DBMS Throughput
While there are known performance trade-offs between database page buffer pool and query execution memory allocation policies, little has been written on the impact of query compi...
Boris Baryshnikov, Cipri Clinciu, Conor Cunningham...
ICCAD
2008
IEEE
150views Hardware» more  ICCAD 2008»
16 years 1 months ago
Performance estimation and slack matching for pipelined asynchronous architectures with choice
— This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the pro...
Gennette Gill, Vishal Gupta, Montek Singh
MSS
2007
IEEE
109views Hardware» more  MSS 2007»
15 years 11 months ago
Performance Evaluation of Multiple TCP connections in iSCSI
Scaling data storage is a significant concern in enterprise systems and Storage Area Networks (SANs) are deployed as a means to scale enterprise storage. SANs based on Fibre Chan...
Bhargava K. Kancherla, Ganesh M. Narayan, K. Gopin...