2032 search results - page 131 / 407 » Improving Java performance using hardware translation |
125
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ICCAD
2005
IEEE
16 years 1 months ago
2005
IEEE
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
154
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ICCD
2007
IEEE
16 years 1 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
138
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DATE
2003
IEEE
15 years 10 months ago
2003
IEEE
We propose a new metric for evaluation of interconnect architectures. This metric is computed by optimal assignment of wires from a given wire length distribution (WLD) to a given...
184
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ASPDAC
1999
ACM
15 years 9 months ago
1999
ACM
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
137
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IWPC
2003
IEEE
15 years 10 months ago
2003
IEEE
1 : This paper describes a prototype tool that facilitates the process of understanding and managing multi-language program dependencies. More specifically, the software tool main...