Sciweavers

2032 search results - page 223 / 407
» Improving Java performance using hardware translation
Sort
View
153
Voted
SAT
2010
Springer
132views Hardware» more  SAT 2010»
15 years 4 months ago
Exploiting Circuit Representations in QBF Solving
Previous work has shown that circuit representations can be exploited in QBF solvers to obtain useful performance improvements. In this paper we examine some additional techniques ...
Alexandra Goultiaeva, Fahiem Bacchus
ICDCS
1997
IEEE
15 years 10 months ago
Multi-threading and Remote Latency in Software DSMs
This paper evaluates the use of per-node multi-threading to hide remote memory and synchronization latencies in a software DSM. As with hardware systems, multi-threading in softwa...
Kritchalach Thitikamol, Peter J. Keleher
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
16 years 12 days ago
Fine-grain thermal profiling and sensor insertion for FPGAs
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...
Somsubhra Mondal, Rajarshi Mukherjee, Seda Ogrenci...
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
16 years 24 days ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
CASES
2007
ACM
15 years 10 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis