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» Improving Java performance using hardware translation
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TEI
2009
ACM
99views Hardware» more  TEI 2009»
16 years 1 months ago
Multi-finger interactions with papers on augmented tabletops
Although many augmented tabletop systems have shown the potential and usability of finger-based interactions and paper-based interfaces, they have mainly dealt with each of them ...
Son Do-Lenh, Frédéric Kaplan, Akshit...
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
16 years 22 days ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
ISCA
2000
IEEE
81views Hardware» more  ISCA 2000»
15 years 10 months ago
Clock rate versus IPC: the end of the road for conventional microarchitectures
The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with tech...
Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckle...
ACMICEC
2004
ACM
171views ECommerce» more  ACMICEC 2004»
15 years 11 months ago
Efficient integration of web services with distributed data flow and active mediation
This paper presents a loosely coupled service-composition paradigm. This paradigm employs a distributed data flow that differs markedly from centralized information flow adopted b...
David Liu, Jun Peng, Kincho H. Law, Gio Wiederhold
MICRO
2008
IEEE
111views Hardware» more  MICRO 2008»
16 years 23 days ago
Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer
It is well recognized that LRU cache-line replacement can be ineffective for applications with large working sets or non-localized memory access patterns. Specifically, in lastle...
Livio Soares, David K. Tam, Michael Stumm