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» Improving Java performance using hardware translation
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CGO
2006
IEEE
16 years 12 days ago
Thread-Shared Software Code Caches
Software code caches are increasingly being used to amortize the runtime overhead of dynamic optimizers, simulators, emulators, dynamic translators, dynamic compilers, and other t...
Derek Bruening, Vladimir Kiriansky, Timothy Garnet...
159
Voted
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
16 years 24 days ago
Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration
Nanowire crossbar is one of the most promising circuit solutions for nanoelectronics. We show nanowire crossbars do not scale well in terms of logic density and speed. We conseque...
Mian Dong, Lin Zhong
DATE
2008
IEEE
167views Hardware» more  DATE 2008»
16 years 24 days ago
Accuracy-Adaptive Simulation of Transaction Level Models
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
Martin Radetzki, Rauf Salimi Khaligh
DATE
2010
IEEE
124views Hardware» more  DATE 2010»
15 years 11 months ago
Reuse-aware modulo scheduling for stream processors
—This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in t...
Li Wang, Jingling Xue, Xuejun Yang
CP
2006
Springer
15 years 10 months ago
A New Algorithm for Sampling CSP Solutions Uniformly at Random
The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) uniformly at random. The main idea is to express the CSP as a factored probability d...
Vibhav Gogate, Rina Dechter