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» Improving Java performance using hardware translation
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DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 11 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
IEEEARES
2006
IEEE
15 years 11 months ago
Secure Enhanced Wireless Transfer Protocol
When IEEE 802.11i draft[1] proposed TKIP, it is expected to improve WEP on both active and passive attack methods. TKIP uses more sophisticated methods to distribute and manage se...
Jin-Cherng Lin, Yu-Hsin Kao, Chen-Wei Yang
MICRO
2006
IEEE
104views Hardware» more  MICRO 2006»
15 years 11 months ago
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the develo...
Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, Jo...
ICCAD
1998
IEEE
105views Hardware» more  ICCAD 1998»
15 years 9 months ago
Fanout optimization under a submicron transistor-level delay model
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...
Pasquale Cocchini, Massoud Pedram, Gianluca Piccin...
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 9 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu