2032 search results - page 268 / 407 » Improving Java performance using hardware translation |
143
Voted
PERCOM
2007
ACM
15 years 4 months ago
2007
ACM
In wireless sensor networks, poor performance or unexpected behavior may be experienced for several reasons, such as trivial deterioration of sensing hardware, unsatisfactory impl...
154
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
131
Voted
ASYNC
2004
IEEE
15 years 8 months ago
2004
IEEE
Register files of microprocessors have often been cited as performance bottlenecks and significant consumers of energy. The robust and modular nature of quasi-delay insensitive (Q...
157
Voted
ISCA
2008
IEEE
15 years 5 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
123
Voted
FPL
2005
Springer
15 years 10 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...