2032 search results - page 278 / 407 » Improving Java performance using hardware translation |
162
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SBACPAD
2007
IEEE
15 years 11 months ago
2007
IEEE
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
126
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MICRO
2006
IEEE
15 years 11 months ago
2006
IEEE
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
148
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ISCA
2002
IEEE
15 years 10 months ago
2002
IEEE
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
137
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DAC
2007
ACM
15 years 9 months ago
2007
ACM
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical...
165
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FPGA
2006
ACM
15 years 8 months ago
2006
ACM
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful def...