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» Improving Java performance using hardware translation
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152
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ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 10 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
ISLPED
2005
ACM
136views Hardware» more  ISLPED 2005»
15 years 10 months ago
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Ha...
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
15 years 9 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
16 years 1 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
117
Voted
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
15 years 11 months ago
A hybrid packet-circuit switched on-chip network based on SDM
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arj...