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» Improving Java performance using hardware translation
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LCN
2008
IEEE
15 years 11 months ago
DiCAP: Distributed Packet Capturing architecture for high-speed network links
— IP traffic measurements form the basis of several network management tasks, such as accounting, planning, intrusion detection, and charging. High-speed network links challenge ...
Cristian Morariu, Burkhard Stiller
DSD
2011
IEEE
309views Hardware» more  DSD 2011»
14 years 4 months ago
FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design
—With the opening up of white spaces, efficient use of the fragmented spectrum - TV white space in particular - has become an extremely important focus of research. Apart from ef...
Rohit Datta, Gerhard Fettweis, Zsolt Kollar, P&eac...
SPAA
2009
ACM
16 years 5 months ago
NZTM: nonblocking zero-indirection transactional memory
This workshop paper reports work in progress on NZTM, a nonblocking, zero-indirection object-based hybrid transactional memory system. NZTM can execute transactions using best-eff...
Fuad Tabba, Mark Moir, James R. Goodman, Andrew W....
126
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ICCD
2006
IEEE
139views Hardware» more  ICCD 2006»
16 years 1 months ago
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Sean Leventhal, Manoj Franklin
DSD
2007
IEEE
120views Hardware» more  DSD 2007»
15 years 11 months ago
Latency Minimization for Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) are a very useful means for modeling and analyzing streaming applications. Some performance indicators, such as throughput, have been studied b...
Amir Hossein Ghamarian, Sander Stuijk, Twan Basten...