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» Improving Java performance using hardware translation
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158
Voted
VTS
2005
IEEE
116views Hardware» more  VTS 2005»
15 years 10 months ago
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
Kartik Mohanram
DAGM
2008
Springer
15 years 6 months ago
Sliding-Windows for Rapid Object Class Localization: A Parallel Technique
Abstract. This paper presents a fast object class localization framework implemented on a data parallel architecture currently available in recent computers. Our case study, the im...
Christian Wojek, Gyuri Dorkó, André ...
COMSIS
2010
15 years 2 months ago
A content-based dynamic load-balancing algorithm for heterogeneous web server cluster
According to the different requests of Web and the heterogeneity of Web server, the paper presents a content-based loadbalancing algorithm. The mechanism of this algorithm is that ...
Lin Zhang, Xiao Ping Li, Su Yuan
128
Voted
ISLPED
2005
ACM
98views Hardware» more  ISLPED 2005»
15 years 10 months ago
Synonymous address compaction for energy reduction in data TLB
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, m...
Chinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, M...
ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
15 years 8 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...