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» Improving Java performance using hardware translation
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ASPLOS
1998
ACM
15 years 9 months ago
Data Speculation Support for a Chip Multiprocessor
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
Lance Hammond, Mark Willey, Kunle Olukotun
DAC
1997
ACM
15 years 9 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
CLUSTER
2010
IEEE
14 years 8 months ago
Middleware support for many-task computing
Many-task computing aims to bridge the gap between two computing paradigms, high throughput computing and high performance computing. Many-task computing denotes highperformance co...
Ioan Raicu, Ian T. Foster, Mike Wilde, Zhao Zhang,...
ICCAD
2007
IEEE
134views Hardware» more  ICCAD 2007»
16 years 1 months ago
Hybrid CEGAR: combining variable hiding and predicate abstraction
ion Chao Wang NEC Laboratories America Hyondeuk Kim University of Colorado Aarti Gupta NEC Laboratories America Variable hiding and predicate abstraction are two popular abstracti...
Chao Wang, Hyondeuk Kim, Aarti Gupta
MICRO
2000
IEEE
107views Hardware» more  MICRO 2000»
15 years 8 months ago
Register integration: a simple and efficient implementation of squash reuse
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential execution using data-dependence relationships. In this...
Amir Roth, Gurindar S. Sohi