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» Improving Java performance using hardware translation
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ASPDAC
2008
ACM
92views Hardware» more  ASPDAC 2008»
15 years 7 months ago
Decomposition based approach for synthesis of multi-level threshold logic circuits
Scaling is currently the most popular technique used to improve performance metrics of CMOS circuits. This cannot go on forever because the properties that are responsible for the ...
Tejaswi Gowda, Sarma B. K. Vrudhula
SRDS
1998
IEEE
15 years 9 months ago
AQuA: An Adaptive Architecture that Provides Dependable Distributed Objects
Dependable distributed systems are difficult to build. This is particularly true if they have dependability requirements that change during the execution of an application, and are...
Michel Cukier, Jennifer Ren, Chetan Sabnis, David ...
LCTRTS
2010
Springer
15 years 2 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
SIGOPS
2010
179views more  SIGOPS 2010»
14 years 11 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
155
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HPCA
2011
IEEE
14 years 8 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...