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» Improving Java performance using hardware translation
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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 9 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
CRV
2006
IEEE
155views Robotics» more  CRV 2006»
15 years 11 months ago
Collaborative Multi-Camera Surveillance with Automated Person Detection
This paper presents the groundwork for a distributed network of collaborating, intelligent surveillance cameras, implemented with low-cost embedded microprocessor camera modules. ...
Trevor Ahmedali, James J. Clark
CODES
2005
IEEE
15 years 10 months ago
Novel architecture for loop acceleration: a case study
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
Seng Lin Shee, Sri Parameswaran, Newton Cheung
ISCAS
2003
IEEE
115views Hardware» more  ISCAS 2003»
15 years 10 months ago
An efficient color compensation scheme for skin color segmentation
Skin color is a useful means for human face detection. In this paper, we propose an efficient color compensation method for skin color segmentation under varying lighting conditio...
Kwok-Wai Wong, Kin-Man Lam, Wan-Chi Siu
117
Voted
FPL
2003
Springer
81views Hardware» more  FPL 2003»
15 years 10 months ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby