2032 search results - page 299 / 407 » Improving Java performance using hardware translation |
149
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MICRO
2002
IEEE
15 years 9 months ago
2002
IEEE
Master/Slave Speculative Parallelization (MSSP) is an execution paradigm for improving the execution rate of sequential programs by parallelizing them speculatively for execution ...
152
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FPL
2001
Springer
15 years 9 months ago
2001
Springer
System and processor architectures depend on changes in technology. Looking ahead as die density and speed increase, power consumption and on chip interconnection delay become incr...
185
Voted
ASPDAC
2007
ACM
15 years 9 months ago
2007
ACM
Dynamic voltage scaling (DVS) circuits have been widely adopted in many computing systems to provide tradeoff between performance and power consumption. The effective use of energ...
142
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ETS
2011
IEEE
14 years 4 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
169
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FPGA
2007
ACM
15 years 11 months ago
2007
ACM
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...