2032 search results - page 325 / 407 » Improving Java performance using hardware translation |
126
Voted
DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
120
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
139
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DSD
2002
IEEE
15 years 9 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
136
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ICCAD
1993
IEEE
15 years 9 months ago
1993
IEEE
We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized “bur...
134
Voted
AICCSA
2007
IEEE
15 years 8 months ago
2007
IEEE
Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In noncontiguous allocation, a ...