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DATE
2006
IEEE
126views Hardware» more  DATE 2006»
15 years 11 months ago
Analysis and modeling of power grid transmission lines
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission ...
J. Balachandran, Steven Brebels, G. Carchon, T. We...
SBACPAD
2005
IEEE
139views Hardware» more  SBACPAD 2005»
15 years 10 months ago
Chained In-Order/Out-of-Order DoubleCore Architecture
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...
Miquel Pericàs, Adrián Cristal, Rube...
ISLPED
2005
ACM
96views Hardware» more  ISLPED 2005»
15 years 10 months ago
Power-optimal repeater insertion considering Vdd and Vth as design freedoms
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion ...
Yu Ching Chang, King Ho Tam, Lei He
ISPD
2005
ACM
153views Hardware» more  ISPD 2005»
15 years 10 months ago
Evaluation of placer suboptimality via zero-change netlist transformations
In this paper we introduce the concept of zero-change transformations to quantify the suboptimality of existing placers. Given a netlist and its placement from a placer, we formal...
Andrew B. Kahng, Sherief Reda
ITC
2003
IEEE
139views Hardware» more  ITC 2003»
15 years 10 months ago
Fault Pattern Oriented Defect Diagnosis for Memories
Failure analysis (FA) and diagnosis of memory cores plays a key role in system-on-chip (SOC) product development and yield ramp-up. Conventional FA based on bitmaps and the experi...
Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung...