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EH
2002
IEEE
105views Hardware» more  EH 2002»
15 years 9 months ago
Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic
The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5GHz have been reported. However, to make the idea practical, serious power management an...
Channakeshav, Kuan Zhou, Russell P. Kraft, John F....
ISCA
2002
IEEE
103views Hardware» more  ISCA 2002»
15 years 9 months ago
Efficient Dynamic Scheduling Through Tag Elimination
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
Dan Ernst, Todd M. Austin
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 9 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
SIGMETRICS
2010
ACM
178views Hardware» more  SIGMETRICS 2010»
15 years 9 months ago
Optimality, fairness, and robustness in speed scaling designs
System design must strike a balance between energy and performance by carefully selecting the speed at which the system will run. In this work, we examine fundamental tradeoffs i...
Lachlan L. H. Andrew, Minghong Lin, Adam Wierman
ASYNC
2000
IEEE
86views Hardware» more  ASYNC 2000»
15 years 9 months ago
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
This paper introduces several new asynchronous pipeline designs which offer high throughput as well as low latency. The designs target dynamic datapaths, both dualrail as well as ...
Montek Singh, Steven M. Nowick