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IPPS
2009
IEEE
15 years 11 months ago
Core-aware memory access scheduling schemes
Multi-core processors have changed the conventional hardware structure and require a rethinking of system scheduling and resource management to utilize them efficiently. However, ...
Zhibin Fang, Xian-He Sun, Yong Chen, Surendra Byna
ESTIMEDIA
2009
Springer
15 years 11 months ago
QoS management of dynamic video tasks by task splitting and skipping
—We have integrated processing with deterministic and non-deterministic resource usage in an overall application and evaluated its performance on a multi-core processor platform....
Rob Albers, Eric Suijs, Peter H. N. de With
NOCS
2008
IEEE
15 years 11 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
ARITH
2007
IEEE
15 years 11 months ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
118
Voted
MSS
2007
IEEE
111views Hardware» more  MSS 2007»
15 years 10 months ago
Enabling database-aware storage with OSD
The ANSI Object-based Storage Device (OSD) standard is a major step toward enabling explicit application­ awareness in storage systems behind a standard, fully­ interoperable in...
Aravindan Raghuveer, Steven W. Schlosser, Sami Ire...