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» Improving Java performance using hardware translation
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NCA
2006
IEEE
15 years 4 months ago
Evolutionary training of hardware realizable multilayer perceptrons
The use of multilayer perceptrons (MLP) with threshold functions (binary step function activations) greatly reduces the complexity of the hardware implementation of neural networks...
Vassilis P. Plagianakos, George D. Magoulas, Micha...
PLDI
2004
ACM
15 years 10 months ago
Cloning-based context-sensitive pointer alias analysis using binary decision diagrams
This paper presents the first scalable context-sensitive, inclusionbased pointer alias analysis for Java programs. Our approach to context sensitivity is to create a clone of a m...
John Whaley, Monica S. Lam
ISSTA
2006
ACM
15 years 10 months ago
The case for analysis preserving language transformation
Static analysis has gained much attention over the past few years in applications such as bug finding and program verification. As software becomes more complex and componentize...
Xiaolan Zhang, Larry Koved, Marco Pistoia, Sam Web...
IEEEPACT
2002
IEEE
15 years 9 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
15 years 10 months ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...