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» Improving Java performance using hardware translation
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FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
15 years 9 months ago
Matching and searching analysis for parallel hardware implementation on FPGAs
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
Pablo Moisset, Pedro C. Diniz, Joonseok Park
ICSE
2005
IEEE-ACM
16 years 4 months ago
Binary refactoring: improving code behind the scenes
We present Binary Refactoring: a software engineering technique for improving the implementation of programs without modifying their source code. While related to regular refactor...
Eli Tilevich, Yannis Smaragdakis
RECOMB
2004
Springer
16 years 5 months ago
A class of edit kernels for SVMs to predict translation initiation sites in eukaryotic mRNAs
The prediction of translation initiation sites (TISs) in eukaryotic mRNAs has been a challenging problem in computational molecular biology. In this paper, we present a new algori...
Haifeng Li, Tao Jiang
WSCG
2004
154views more  WSCG 2004»
15 years 6 months ago
Emulating an Offline Renderer by 3D Graphics Hardware
3D design software has since long employed graphics chips for low-quality real-time previewing. But their dramatically increased computing power now paves the way to accelerate th...
Jörn Loviscach
ISM
2008
IEEE
110views Multimedia» more  ISM 2008»
15 years 11 months ago
A Hardware-Independent Fast Logarithm Approximation with Adjustable Accuracy
Many multimedia applications rely on the computation of logarithms, for example, when estimating log-likelihoods for Gaussian Mixture Models. Knowing of the demand to compute loga...
Oriol Vinyals, Gerald Friedland