Sciweavers

187 search results - page 16 / 38
» Improving Memory Energy Using Access Pattern Classification
Sort
View
92
Voted
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 2 months ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
QEST
2007
IEEE
15 years 3 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
67
Voted
VLDB
2004
ACM
143views Database» more  VLDB 2004»
15 years 3 months ago
Clotho: Decoupling memory page layout from storage organization
As database application performance depends on the utilization of the memory hierarchy, smart data placement plays a central role in increasing locality and in improving memory ut...
Minglong Shao, Jiri Schindler, Steven W. Schlosser...
ICPP
2002
IEEE
15 years 2 months ago
Analysis of Memory Hierarchy Performance of Block Data Layout
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In...
Neungsoo Park, Bo Hong, Viktor K. Prasanna
ICWS
2009
IEEE
15 years 6 months ago
Adaptive Prefetching Scheme Using Web Log Mining in Cluster-Based Web Systems
The main memory management has been a critical issue to provide high performance in web cluster systems. To overcome the speed gap between processors and disks, many prefetch sche...
Heung Ki Lee, Baik Song An, Eun Jung Kim