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» Improving Memory Energy Using Access Pattern Classification
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DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 4 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
14 years 1 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
FPL
2004
Springer
164views Hardware» more  FPL 2004»
15 years 1 months ago
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors
Abstract. In Reconfigurable Systems-On-Chip (RSoCs), operating systems can primarily (1) manage the sharing of limited reconfigurable resources, and (2) support communication betwe...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
72
Voted
PODC
2009
ACM
15 years 10 months ago
Preventing versus curing: avoiding conflicts in transactional memories
Transactional memories are typically speculative and rely on contention managers to cure conflicts. This paper explores a complementary approach that prevents conflicts by schedul...
Aleksandar Dragojevic, Rachid Guerraoui, Anmol V. ...
CHI
2005
ACM
15 years 10 months ago
Using intimacy, chronology and zooming to visualize rhythms in email experience
Experiences of intimacy and connectedness through social networks are vital to human sense of well-being. We live in an electronic habitat. Electronic mail functions as a medium o...
Mirko Mandic, Andruid Kerne