328 search results - page 57 / 66 » Improving Performance of Small On-Chip Instruction Caches |
INFOCOM
1992
IEEE
15 years 1 months ago
1992
IEEE
The current Internet is based on a stateless (datagram) architecture. However, many recent proposals rely on the maintenance of state information within network routers, leading t...
DAC
2000
ACM
15 years 10 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
IWMM
2009
Springer
15 years 4 months ago
2009
Springer
Good spatial locality alleviates both the latency and bandwidth problem of memory by boosting the effect of prefetching and improving the utilization of cache. However, convention...
102
Voted
CF
2006
ACM
15 years 3 months ago
2006
ACM
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
91
Voted
DAMON
2006
Springer
14 years 11 months ago
2006
Springer
Recent performance improvements in storage hardware have benefited bandwidth much more than latency. Among other implications, this trend favors large B-tree pages. Recent perform...