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» Improving Placement under the Constant Delay Model
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GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
15 years 2 months ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
83
Voted
ICRA
2010
IEEE
172views Robotics» more  ICRA 2010»
14 years 8 months ago
Coordinated multi-robot real-time exploration with connectivity and bandwidth awareness
— While there has been substantial progress for multi-robot exploration of an unknown area, little attention has been given to communication, especially bandwidth constraints in ...
Yuanteng Pei, Matt W. Mutka, Ning Xi
81
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ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 2 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
ICMCS
2005
IEEE
119views Multimedia» more  ICMCS 2005»
15 years 3 months ago
Evaluation of the Interleaved Source Coding (ISC) Under Packet Correlation
Network impairments such as delay and packet losses have severe impact on the presentation quality of many predictive video sources. Prior researches (e.g., [1]-[3][5]-[9][11]-[13...
Jin Young Lee, Hayder Radha
ESA
2009
Springer
99views Algorithms» more  ESA 2009»
15 years 4 months ago
Minimizing Maximum Response Time and Delay Factor in Broadcast Scheduling
We consider online algorithms for pull-based broadcast scheduling. In this setting there are n pages of information at a server and requests for pages arrive online. When the serv...
Chandra Chekuri, Sungjin Im, Benjamin Moseley