196 search results - page 23 / 40 » Improving Placement under the Constant Delay Model |
ITNG
2007
IEEE
15 years 3 months ago
2007
IEEE
In networks-on-chip (NoC) designs, delay variations and crosstalk noise have become a serious issue with the continuously shrinking geometry of semiconductor devices and the incre...
101
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ISPD
2005
ACM
15 years 3 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
85
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DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
PDP
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper shows a new distributed algorithm for deadlock detection and resolution under the single-resource request model that highly improves the complexity measurements of prev...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
Interconnect tuning is an increasingly critical degree of freedom in the physical design of high-performance VLSI systems. By interconnect tuning, we refer to the selection of lin...