99 search results - page 10 / 20 » Improving Program Efficiency by Packing Instructions into Re... |
73
Voted
LCPC
1998
Springer
15 years 1 months ago
1998
Springer
Techniques for aggressive optimization and parallelization of applications can have the side-effect of introducing copy instructions, register-to-register move instructions, into t...
TSP
2008
14 years 9 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
VLSISP
2008
14 years 9 months ago
2008
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
IEEEPACT
2003
IEEE
15 years 2 months ago
2003
IEEE
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...