99 search results - page 14 / 20 » Improving Program Efficiency by Packing Instructions into Re... |
ASPLOS
2008
ACM
14 years 11 months ago
2008
ACM
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
FCCM
2003
IEEE
15 years 2 months ago
2003
IEEE
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
ISCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Dynamic information flow tracking (also known as taint tracking) is an appealing approach to combat various security attacks. However, the performance of applications can severely...
103
Voted
ASPLOS
2006
ACM
15 years 1 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...
JSA
2000
14 years 9 months ago
2000
In this article, the problem of finding a tight estimate on the worst-case execution time (WCET) of a real-time program is addressed. The analysis is focused on straight-line code...