99 search results - page 4 / 20 » Improving Program Efficiency by Packing Instructions into Re... |
MICRO
2008
IEEE
15 years 4 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
69
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HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
122
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EMSOFT
2004
Springer
15 years 3 months ago
2004
Springer
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...
APPT
2009
Springer
15 years 4 months ago
2009
Springer
SIMD extension is one of the most common and effective technique to exploit data-level parallelism in today’s processor designs. However, the performance of SIMD architectures i...
68
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Application-specific instruction-set extensions (custom instructions) help embedded processors achieve higher performance. Most custom instructions offering significant performanc...