99 search results - page 9 / 20 » Improving Program Efficiency by Packing Instructions into Re... |
ISSS
1996
IEEE
15 years 1 months ago
1996
IEEE
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
112
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LCPC
2000
Springer
15 years 1 months ago
2000
Springer
Embedded systems consisting of the application program ROM, RAM, the embedded processor core, and any custom hardware on a single wafer are becoming increasingly common in applicat...
CATA
2004
14 years 11 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
122
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RTAS
1996
IEEE
15 years 1 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
SBACPAD
2005
IEEE
15 years 3 months ago
2005
IEEE
Complexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, ...